  -- Procesor - plik glowny
 
 library IEEE;
 use IEEE.Std_Logic_1164.all;
 
 entity processor2 is
   port (CLK, RST   : in std_logic);
 end entity processor2;
 
 architecture processor2_struct of processor2 is
   signal DATA_BUS, ROM_OUT, RI_OUT, RN_OUT, REGX_OUT, REGY_OUT, GA_PC : std_logic_vector(7 downto 0);
   signal DATA_BUS3, FLAGS_IN : std_logic_vector(3 downto 0);
   signal ADDRESS_BUS, ROM_ADDR, PC_OUT, CU_ARG1, CU_ARG2 : std_logic_vector(3 downto 0);
   signal GA : std_logic_vector(2 downto 0);
   signal ALU_INSTR, CU_INSTR, CU_ADRARG1, CU_ADRARG2, ERROR : std_logic_vector(1 downto 0);
   signal ROM_R, ROM_LAE, ROM_IE, ROM_OE : std_logic;
   signal PC_RESET, PC_INCR, RI_LAE, RN_LAE : std_logic;
   signal REGX_IE, REGX_OE, REGY_IE, REGY_OE, FLAGS_IE, FLAGS_OE, ALU_OE, ALU_START : std_logic;
   signal R1_IE, R1_OE,R2_IE, R2_OE,R3_IE, R3_OE,R4_IE, R4_OE,R5_IE, R5_OE,R6_IE, R6_OE,RTMP_IE, RTMP_OE: std_logic;
   signal CU_CLOCK, CU_RESET, DE_DECODE : std_logic;
 begin
   CU_CLOCK <= CLK;
   CU_RESET <= RST;
 
   
    -- Pamiec programu
   ROM: entity work.ROM
     port map (
        ADDRESS => ROM_ADDR,
        OE      => ROM_R,
        DATA    => ROM_OUT
     );
   
   -- Rejestr adresowy pamieci programu  
   RegROMAddress: entity work.REG4_LATCH
     port map (
        LAE     => ROM_LAE,
        DATAIN  => ADDRESS_BUS,
        DATAOUT => ROM_ADDR
     );
       
   -- Bufor danych pamieci programu
   RegROMfer: entity work.REG8
     port map (
        IE      => ROM_IE,
        OE      => ROM_OE,
        DATAIN  => ROM_OUT,
        DATAOUT => DATA_BUS
     );
     
 ----------------------------------
 
   -- Rejestr X przy ALU
   RegX: entity work.REG8_LATCH
     port map (
        LAE     => REGX_IE,
        DATAIN  => DATA_BUS,
        DATAOUT => REGX_OUT
     );
     
   -- Rejestr Y przy ALU
   RegY: entity work.REG8_LATCH
     port map (
        LAE     => REGY_IE,
        DATAIN  => DATA_BUS,
        DATAOUT => REGY_OUT
     );
 
   -- ALU
   ALU: entity work.ALU2
     port map (
       X       => REGX_OUT,
       Y       => REGY_OUT,
       INSTR   => ALU_INSTR,
       ALUOUT  => DATA_BUS,
       OE      => ALU_OE, -- cu
       START   => ALU_START,
       FLAGOUT => FLAGS_IN,
       FLAGW   => FLAGS_IE
     );
     
   -- Rejestr flag
   Flags: entity work.FLAGS
     port map (
       IE       => FLAGS_IE,
       OE       => FLAGS_OE, -- cu
       FLAGSIN  => FLAGS_IN,
       FLAGSOUT => DATA_BUS3
     );
   DATA_BUS3 <= DATA_BUS(3 downto 0);
 
 ----------------------------------
 
   -- Jednostka centralna
   CU2: entity work.CU2
     port map (
       CLOCK         => CU_CLOCK,
       RESET         => CU_RESET,
       INSTR         => CU_INSTR,
       ADRARG1       => CU_ADRARG1,
       ADRARG2       => CU_ADRARG2,
       ARG1          => CU_ARG1,
       ARG2          => CU_ARG2,
       CU_GA         => GA,
       CU_ROM_LAE    => ROM_LAE,
       CU_ROM_R      => ROM_R,
       CU_ROM_IE     => ROM_IE,
       CU_ROM_OE     => ROM_OE,
       CU_PC_INCR    => PC_INCR,
       CU_PC_RESET   => PC_RESET,
       CU_RI_LAE     => RI_LAE,
       CU_RN_LAE      => RN_LAE,
       CU_DE_DECODE  => DE_DECODE,
       CU_REGX_IE    => REGX_IE,
       CU_REGY_IE    => REGY_IE,
       CU_ALU_INSTR  => ALU_INSTR,
       CU_ALU_START  => ALU_START,
       CU_ERROR      => ERROR,
       CU_R1_IE      => R1_IE,
       CU_R1_OE      => R1_OE,
       CU_R2_IE      => R2_IE,
       CU_R2_OE      => R2_OE,
       CU_R3_IE      => R3_IE,
       CU_R3_OE      => R3_OE,
       CU_R4_IE      => R4_IE,
       CU_R4_OE      => R4_OE,
       CU_R5_IE      => R5_IE,
       CU_R5_OE      => R5_OE,
       CU_R6_IE      => R6_IE,
       CU_R6_OE      => R6_OE,
       CU_RTMP_IE    => RTMP_IE,
       CU_RTMP_OE      => RTMP_OE,
       CU_ALU_OE      => ALU_OE     
     );
     
   -- Dekoder
   Decoder: entity work.DECODER2
     port map (
       DECODE      => DE_DECODE,   
       INSTRUCTION => RI_OUT,           
       INSTR       => CU_INSTR,
       ADRARG1     => CU_ADRARG1,
       ADRARG2     => CU_ADRARG2,
       ARG1        => CU_ARG1,
       ARG2        => CU_ARG2  
     );
 
   -- Rejestr instrukcji
   RegInstr: entity work.REG8_LATCH
     port map (
        LAE     => RI_LAE,
        DATAIN  => DATA_BUS,
        DATAOUT => RI_OUT
     );
 
 ----------------------------------
 
   -- Generator adresu
   GENADD: entity work.GA
     port map (
       INPUT0 => GA_PC,
       INPUT1 => RN_OUT,
       INPUT2 => "ZZZZZZZZ",
       INPUT3 => "ZZZZZZZZ",
       INPUT4 => "ZZZZZZZZ",
       INPUT5 => "ZZZZZZZZ",
       INPUT6 => "ZZZZZZZZ",
       INPUT7 => "ZZZZZZZZ",
       OUTPUT => ADDRESS_BUS,
       S => GA
     );
     GA_PC(3 downto 0) <= PC_OUT;
     
   -- Licznik programu
   ProgCounter: entity work.PROG_COUNTER
     port map (
        RESET  => PC_RESET,
        INCR   => PC_INCR,
        CLOCK  => CU_CLOCK,
        OUTPUT => PC_OUT
     );
     
   -- Rejestr natychmiastowy
   RegImm: entity work.REG8_LATCH
     port map (
        LAE     => RN_LAE,
        DATAIN  => DATA_BUS,
        DATAOUT => RN_OUT
     );
  -----------------------------------------
  -- Rejestry tymczasowy(RegTMP) i Reg1 do Reg6
  RegTMP: entity work.REG8
    port map (
        IE      => RTMP_IE,
        OE      => RTMP_OE,
        DATAIN  => DATA_BUS,
        DATAOUT => DATA_BUS
     );
  Reg1: entity work.REG8
    port map (
        IE      => R1_IE,
        OE      => R1_OE,
        DATAIN  => DATA_BUS,
        DATAOUT => DATA_BUS
     );
 Reg2: entity work.REG8
    port map (
        IE      => R2_IE,
        OE      => R2_OE,
        DATAIN  => DATA_BUS,
        DATAOUT => DATA_BUS
     );
Reg3: entity work.REG8
    port map (
        IE      => R3_IE,
        OE      => R3_OE,
        DATAIN  => DATA_BUS,
        DATAOUT => DATA_BUS
     );
Reg4: entity work.REG8
    port map (
        IE      => R4_IE,
        OE      => R4_OE,
        DATAIN  => DATA_BUS,
        DATAOUT => DATA_BUS
     );
Reg5: entity work.REG8
    port map (
        IE      => R5_IE,
        OE      => R5_OE,
        DATAIN  => DATA_BUS,
        DATAOUT => DATA_BUS
     );
Reg6: entity work.REG8
    port map (
        IE      => R6_IE,
        OE      => R6_OE,
        DATAIN  => DATA_BUS,
        DATAOUT => DATA_BUS
     );
 end;
 
 
 
 